Design Compiler SYNOPSYS VANTAGE VHDL

We present a solution to the veri cation problem of high-level synthesis. The high-level synthesis system CALLAS takes as input an algorithmic speci cation, in VHDL, and produces as output an EDIF netlist. Both, the speci cation and the generated netlist can be interpreted as nite state machine descriptions. Then, in this context, the veri cation problem is reduced to proving the behavioral equivalence of both machines. For this equivalence proof we use the symbolic veri er of the CVE System (CVE = Circuit Veri cation Environment). Recent improvements of the veri er allowed equivalence proofs of machines with up to 260 binary state variables.